Pulse position modulated alarm system

ABSTRACT

A system for transmitting, via a radio link to a central station, alarm indications at a plurality of monitored stations. Each monitored station includes a different code identification number which controls pulse position modulation of a carrier that is transmitted to the central station only in response to an alarm condition being sensed. The type of alarm condition being sensed also pulse position modulates the carrier transmitted from the peripheral station to the central station. At the central station, the carrier is received and the pulse position modulated pulses are detected and processed to provide indications of the identity of the monitored station at which the alarm condition was sensed, as well as the cause of the sensed alarm.

Wootton 1 Sept. 5, 1972 PULSE POSITION MODULATED ALARM SYSTEM 3,519,7497/ 1 970 Kline 179/5 X Primary Examiner-Donald J. Yusko [72] Inventor:Thomas S. Wootton, El Paso, Tex. Attorney-Hyman Hurvltz [7 3] Assignee:Baldwin Electronics, Inc., Little 7 Rock, Ark. [57] ABSTRACT Filed: 1970A system for transmitting, via a radio link to a central [2]] APPL No:103,203 station, alarm indications at a plurality of monitored stations.Each monitored station includes a difierent code identification numberwhich controls pulse posi- U-Sa R, a is to [51] Int. Cl. ..H04q 1/42central Station only in response to an alarm condition [58] Field ofSearch..340/224, 207, 183, 164 R, 150; being Sensed The type of alarmcondition being 343/203; 325/143 sensed also pulse position modulatesthe carrier transmitted from the peripheral station to the central sta-[56] References C'ted tion. At the central station, the carrier isreceived and UNITED STATES PATENTS the pulse position modulated pulsesare detected and processed to provide indications of the identity of the3,377,585 4/1968 Magnln ..340/ 183 X monitored Station at which thealarm condition was 3,394,349 7/ 1968 Day ..340/163 sensed as as thecause f the sensed alanm 3,466,605 9/1969 Shoenwntz ..340/ 151 3,518,6286/1970 Giel et al. ..340/ 150 X 13 Claims, 17 Drawing FiguresBATTERIESEp 'L 53%;? amrgg mes l I 4% INPUT cuzcuns 33min. DETECTORS:25a EEGULQTUR up \D TEN CHANNELS I I l mmusmN L16 l ,r UJATER I FNLUREl I 1 mmcl zgggmu T F T ?.l l I22 rm. 1 CODE l.D.NUMBER Mooutm'mNGENERQTUIZ GENERATOR oscmn'rnn l| 9 l v 23 ANTENNA T I +0 QMPUTUDE IMODULATOR i l l i cvxsrm. l CONTROLLED Tanusmmen oscmmmz '24PATENTEIJSEP 1m 8.888.888

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E a my AT TO RNEYS PULSE POSITION MODULATED ALARM SYSTEM The presentinvention relates generally to systems for monitoring alarm conditionsat a plurality of peripheral stations and, more particularly, to asystem for transmitting to a central station pulse position modulatedsignals indicative of the identity of a peripheral station sensing analarm condition.

Briefly described, the alarm system of the present invention includes aplurality of peripheral stations which transmit via a radio link, ratherthan a hard wire link, signals indicative of the identity of aperipheral station where an alarm occurs, as well as the nature of thealarm. The use of a radio link, rather than a hard wire link as isgenerally the practice in the art, is advantageous because the need fora permanent installation is obviated and because of the ability tomonitor mobile sites. A radio link is established between a particularperipheral, monitored station and the central station only in responseto an alarm condition being sensed at the peripheral station. Inresponse to an alarm condition being sensed at a particular peripheralstation, a transmitter at the peripheral station is activated for anumber of predetermined time periods separated from each other by arelatively long time interval. During each of the time periods a signalis repeatedly transmitted from the peripheral station to indicate theidentity of the peripheral station, as well as the alarm condition beingsensed. Thereby, a high integrity link between the peripheral andcentral stations is established. By providing relatively long timeintervals between adjacent transmissions a number of peripheral stationscan transmit data substantially simultaneously to the central stationvia a single radio band. In practice, it has been found that in excessof 80 peripheral stations can be monitored satisfactorily in this mannerand studies indicate that a considerably greater number of stations canbe satisfactorily handled.

Each peripheral station is identified with a different code number thatis converted into a discrete valued pulse position modulated signal inresponse to an alarm condition being sensed. The source of the alarmcondition sensed is also converted into a pulse position modulatedsignal that is in a wavetrain including the peripheral stationidentification signal. One of the pulses, a master pulse of thewavetrain which comprises a data frame, has an identifiablecharacteristic different from all of the other pulses of the frameenabling it to be detected at the central station and be used forenabling the master pulse to be identified with a particular bit usedfor signifying station identification or a sensed alarm.

At the central station frames from the peripheral stations are received,detected and processed to establish peripheral station identificationand the source of the alarm at the particular peripheral station.Processing the signal at the central station involves detecting theidentifiable characteristic of the frame master pulse received from theperipheral station. In response to the identifiable characteristic ofthe master pulse being detected, the time interval amongst the pulses isdetermined by gating a clock signal to a plurality of counters, at leastone of which is provided for each of the pulses of the frame. Theinterval between adjacent pulses of succeeding frames is employed forindicating the magnitude of a data bit at the transmitting station.

Because of this factor, operations are performed during the first bit ofeach frame and the possibility of inaccuracies in measuring the durationof the first bit of each frame occurs. To obviate this possibility, thefirst bit of successive frames is fed to a pair of counters, one ofwhich is utilized during a first frame and the second of which isemployed during the succeeding frame. The two counters feed a commonoutput display network, whereby the first data bit is presented inexactly the same form as other bits.

It is, accordingly, an object of the present invention to provide a newand improved system for monitoring at a central station alarm conditionsexisting at a plurality of peripheral stations.

Another object of the present invention is to provide a new and improvedsystem for transmitting to a central station, via a radio link,indications of the identity of a peripheral station responding to analarm condition, as well as indicative of the nature of the alarm beingsensed.

Still another object of the invention is to provide a new and improvedsystem for monitoring alarm conditions at a plurality of peripheralstations wherein indications of the station identity and nature of thecause of the alarm are transmitted to a central station by pulseposition modulation on a radio link.

Still another object of the invention is to provide a new and improvedalarm system employing pulse position modulation for identification of aperipheral station, wherein adjacent bits between different frames ofdata can be employed without affecting the accuracy of data processed ata central station responsive to the peripheral stations.

The above and still further objects, features and advantages of thepresent invention will become apparent upon consideration of thefollowing detailed description of one specific embodiment thereof,especially when taken in conjunction with the accompanying drawings,wherein:

FIG. 1 is a block diagram of a preferred embodiment of a peripheralstation in accordance with the present invention;

FIGS. 2a and 2b, taken together, are a circuit diagram of the stationillustrated in FIG. 1;

FIGS. 3a-3k are waveforms useful in describing the operation of thesystem;

FIG. 4 is a block diagram of a preferred embodiment of a central stationin accordance with a preferred embodiment of the present invention;

FIG. 5 is a circuit diagram of a portion of the central stationillustrated in FIG. 4;

FIG. 5a is a circuit diagram of another portion of the central stationillustrated in FIG. 4; and

FIG. 6 is a circuit diagram of another portion of the system illustratedin FIG. 4.

The block diagram, FIG. 1, of an exemplary peripheral station issubstantially the same for all stations. The only differences betweenthe different peripheral stations are that each is provided with adifferent identification code number and some may be provided with alarmsensors not included at other peripheral stations. Therefore, adescription of one peripheral station sufiices for all others.

. The peripheral station, FIG. 1, includes a plurality, not in excess of10, of alarm sensor stations, each of which may include a number ofdetectors. Each sensor station derives binary or on-off signals inresponse to occurrences, at a site where the station is located, of, forexample: intrusion into the premises; fire; smoke; water; shock; powerfailure; and refrigeration loss. Each of sensor stations 1-10 normallyderives a binary zero signal, but in response to an alarm conditionbeing sensed derives a binary one signal. Sensor stations l-10 areenergized by dc. power supply 12 under normal operating conditions. Inthe event of failure of power supply 12, which is energized by a U5volt, 60 Hertz source, sensor stations l-l are energized by a batterypower supply 13 that is normally charged by power supply 12.

Power from supply 12 or battery supply 13 is coupled to remainingcircuitry in the peripheral station through electronic switch 14 andregulator 15 only in response to a binary one signal produced by one ormore of sensor stations 110. To the end, output signals from sensorstations l10 are combined and fed to electronic switch 14 to actuate theswitch into a conducting state for a predetermined time interval, on theorder of 3 minutes, after initial sensing of an alarm condition. Duringeach of these 3-minute intervals, electronic switch 14 produces keyedvoltages on lead 16 to enable r.f. transmitter 17 to be energized for30-second periods with a duty cycle of approximately 33 percent, wherebytransmitter 17 is keyed on for l0-second intervals and keyed off for20'second intervals. During a 3-minute interval, transmitter 17 istherefore keyed to an on condition for six l0-second periods. Duringeach of the lO-second periods, transmitter 17 is supplied with at leastframes of data, each of which is less than one second in duration. Eachdata frame includes pulse position modulated bits, the positions ofwhich indicate the code identification number of the peripheral stationand a number associated with the sensor station deriving a binary onesignal. By repeatedly transmitting the same data at spaced intervalsover the relatively long time interval of 3 minutes, signal integritybetween the peripheral station and a central station, described infra,is maintained while allowing a large number of peripheral stations totransmit on the same frequency to the central station.

Signals derived from sensor stations l-l0 are fed via bus 18 to codegenerator 19, which generates a pulse position output having only one ofIO discrete values. The pulse position signal generated by codegenerator 19 in response to signals applied to the code generator on bus18 indicates which one of the 10 sensor stations at the peripheralstation is activated into a binary one state. The pulse position isrepresented by the separation between the first and second pulses of afive-bit frame. The first pulse bit in each frame, termed a masterpulse, has an identifiable characteristic different from all other bitswithin a frame, such as a time duration greater than any of the otherbits in a frame.

Code generator 19 also responds to identification number generator 21which supplies control signals to code generator 19 in response to powerbeing supplied to the number generator through switch 14 and regulator15. The identification number generator 21 included at each peripheralstation is different, with each station being assigned a differentnumber which can possibly range from 0000 to 9999. To this end,identification number generator 21 includes circuitry for deriving fourchannels or bits, capable of having any of the discrete levels betweenzero and nine. The four bits derived by number generator 21 are suppliedto code generator 19 to control the relative pulse positions of thesecond through fifth bits or channels of each frame and the fifth bit ofthat frame and the first bit of the next succeeding frame. Thereby, thepulse interval between the second and third, third and fourth, fourthand fifth bits of each frame and the fifth and first bits of succeedingframes are controlled by the four bits supplied to code generator 19 bynumber generator 21. During each data frame, code generator 19 thereforederives a first binary one level having a relatively long time durationfollowed by second, third, fourth and fifth relatively short durationbinary one levels. Between each of the binary one levels derived by codegenerator 19 a binary zero level is derived. A binary zero level is alsoderived between the fifth binary one level of each frame and the firstbinary one level of the next succeeding frame, whereby the time periodbetween the leading edges of the last pulse of a first frame and thefirst pulse of the next succeeding frame is a pulse position andindicative of one of the discrete values fed to code generator 19. Byusing this pulse position technique, time spacing between adjacentframes is minimized and the need for time synchronization betweenadjacent frames is eliminated.

The binary one and zero levels derived by code generator 19 control thefrequency of tones derived by transmitter 17. To this end, the output ofcode generator 19 is supplied to modulation oscillator 22 which derivesan audio frequency tone of a first frequency, 1.4 KHz, in response to abinary zero level being supplied thereto and a second audio tone, offrequency 1.5 KHz, in response to a binary one level being fed thereto.The discrete frequency tones generated by oscillator 22 are fed toamplitude modulator 23 for transmitter 17. Transmitter 17 is alsoresponsive to crystal controlled oscillator 24 so that it derives, whilekeyed on, 10 frames of r.f. signals that selectively amplitude modulatethe carrier frequency of oscillator 24 by either 1.4 or 1.5 KHz. Bycontinuously transmitting a.m. signals having only one or two modulationfrequencies throughout a IO-frame interval, system noise is minimizedand receiver detection problems simplified.

To enable each remote station to have substantially the same equipment,as described, the output of transmitter 17 is supplied to anomnidirectional, low-gain antenna 25. Power supplied by transmitter 17to antenna 25 is of a sufficiently high level to enable facile signaldetection at the central station.

Reference is now made to FIGS. 2a and 2b, detailed circuit diagram ofcomponents illustrated in the block diagram of FIG. 1, wherein sensorstations 1 and 2 are illustrated as intrusion detection devices. Theremaining sensor stations 3-10 are identical to sensor stations 1 and 2,with the only possible difference being in the type of transducersprovided to establish binary one and zero levels; thereby, there is noneed to illustrate details of the other sensor stations.

Sensor station 1 includes a pair of conducting tapes 31 and 32 whichserve as transducers for determining if an intrusion has been made intoa protected area.

Tapes 31 and 32 normally provide conducting paths to electrodes ofnormally conducting NPN transistor 33 and are mutually insulated fromeach other. When an intrusion occurs into a region being protected bytapes 31 and 32, one or both of the tapes are either open-circuited orthe two tapes are short-circuited together to change the bias potentialapplied to electrodes of transistor 33 whereby the transistor isrendered into a cut-off condition. In response to transistor 33 beingat:- tivated into a cut-off condition, the voltage of the transistorcollector increases in magnitude. The increase in the collector voltageof transistor 33 is coupled through diode 34 and a filter or delaynetwork including shunt resistor 35 and shunt capacitor 36, allowing thecapacitor to charge. In response to capacitor 36 being charged for apredetermined time interval a voltage of sufficient magnitude is derivedthereby to enable activation of latch circuit 37 into a conducting lowimpedance state. The filter circuit comprising resistor 35 and capacitor36 thereby prevents false tripping of latch network 37 in response tonoise pulses which occasionally are derived at the collector oftransistor 33.

Latch network 37 is normally biased by the collector voltage oftransistor 33 into a nonconducting state and is activated into aconducting state as indicated supra. The conducting state of latch 37 ismaintained until the latch is reset, either manually or after apredetermined time interval, on the order of 3 minutes. Latch network 37is a regenerative network including PNP transistor 38 and NPN transistor39. The emitter of transistor 38 is responsive to the voltage developedacross the filter network including resistor 35 and capacitor 36. Thecollector of transistor 38 is short-circuited to the base of transistor39, the collector of which is connected in the regenerative network backto the base of transistor 38. With this circuit arrangement, asufficiently high voltage applied to the emitter of transistor 38activates both of transistors 38 and 39 into a conducting state which ismaintained until the current at the emitter of transistor 38 is reducedto a predetermined level by a reset action.

Latch 37 functions in conjunction with capacitor 36 to develop a suddendecrease in the voltage across resistor 35 immediately after the latchhas been triggered or activated. This is because latch 37, once fired,establishes a low impedance path across capacitor 36 to suddenly reducethe voltage across the capacitor. Since the low impedance path ismaintained across capacitor 36 as long as the latch is energized nofurther sudden voltage changes can be developed across capacitor 36until the latch is reset. If the alarm condition still exists when thecurrent at the emitter of transistor 38 is reduced by the reset action,latch 37 remains in the triggered state by virtue of the currentsupplied thereto through diode 34. Deactivation of triggered latch 37can therefore only occur in response to the alarm condition beingremedied and reset action simultaneously occurring. Thereby, only onesudden change in the voltage across capacitor 36 can be derived inresponse to each alarm condition. This is desirable to preclude repeatedtransmission of the same information from the same peripheral station,whereby a large number of peripheral stations can be monitored, eachwith the same carrier transmission frequency.

Sudden changes at the input of latch 37, which therefore can occur onlyin response to sensor station 1 responding to an intrusion, are ac.coupled via capacitor 41 to latching network 42 that controls activationof switch 14. To this end, the emitter of transistor 38 is connected viacapacitor 41 and diode network 43 through manually activated day/nightswitch 44 to the input of latch 42, at the junction between the base oftransistor 45 and collector of transistor 46. Day/night switch 44 isactivated by a subscriber at the peripheral station to connect sensorstation 1 in the circuit only while it is desired to have the premisesguarded against intrusion, which generally occurs only when thesubscriber is not present at the premises. Day/night switches 44 are notprovided for sensor stations that must be operative while the premisesare being occupied by the subscriber: examples of detectors at suchsensor stations are fire detector, smoke detector, water detector andrefrigeration loss detector.

Sensor station 1 is provided with a precision resistor 51 that isselectively connected in circuit with code generator 19 in response tolatch 37 being activated into a conducting state by intrusion beingdetected by sensor 1. Resistor 51 is connected to code generator 19during a predetermined time interval or channel within each of the dataframes. To this end, resistor 51 is connected to the collector of NPNtransistor 52, the emitter of which is connected via diode 53 to thecollector of transistor 39, whereby in response to latch 37 beingactivated transistor 52 is activated into a conducting state in responseto a positive bias voltage being applied to the base thereof. If latch37 is not energized into a conducting state, transistor 52 is cut offregardless of the bias voltage applied to its base electrode. Inresponse to transistor 52 being in a conducting state, a circuit path isestablished via bus 18 from ground, at the emitter of transistor 39, toresistor 51 and the input of code generator 19. A similar circuit isprovided in each of the other sensors 2-10 in response to these sensorsdetecting alarm conditions. The valve of resistor 51 at each of thedifferent sensors, however, is different, whereby a different value ofresistance is connected by an activated sensor to number generator 21.The values of the precision resistors are selected so that l0 differentdiscrete pulse positions, one for each of the sensors, can be derived bycode generator 19.

Continuing now with the description of the circuitry for controllingpower supply switch 14, latch 42 is activated into a conducting state inresponse to a pulse being supplied thereto through any of the capacitors41 of the several sensors. In response to a sudden change negative goingvoltage change across capacitor 36, PNP transistor 55, which functionsas regulator 15, is activated into a conducting state to control biaslevels applied to the bases of NPN power switching transistors 56 and57, having collectors connected to dc. power supply line 460.Transistors 55-57 are normally in a cut-off condition, whereby thecircuits energized through them are normally in an unpowered condition;these circuits are: transmitter 17, code generator 19, identificationnumber generator 21, modulation oscillator 22, amplitude modulator 23,and crystal controlled oscillator 24. DC. power is supplied via line 460to transistors 55-57 by a power supply responsive to a 1 volt, 60 Hertza.c. source that is fed to transformer 58 and converted to d.c. byrectifier 59. The d.c. output voltage across rectifier 59 and filtercapacitors 61 charges batteries 62 so that these batteries areconstantly maintained in a state of readiness in the event of an a.c.power failure. A tap between capacitors 61 and batteries 62 is connectedin parallel to the emitter of regulating transistor 55 and switchtransistors 56 and 57 to supply voltages of the appropriate level to thevarious circuits energized thereby.

In response to transistors 56 and 57 being activated into a conductingstate, the peripheral station is allowed to remain in an energized statefor only a predetermined time interval, preferably a relatively longinterval, such as 3 minutes. To this end, switch 14 includes a 3-minutetimer comprising series connected resistors 58, capacitor 59 and loadresistor 60, all of which are connected in shunt with the emitter oftransistor 56. The values of resistors 58 and capacitor 59 are selectedto provide an r.c. time constant on the order of 3 minutes, whereby thevoltage across capacitor 59 after 3 minutes reaches a predeterminedlevel which can activate a trigger circuit including unijunctiontransistor 62. In response to the eta value (the intrinsic standoffratio of a unijunction transistor) of unijunction 62 being reached,capacitor 59 is discharged through the unijunction transistor, wherebythere is derived a relatively short duration pulse across load resistor60. The eta value of transistor 62 can, however, be reached with theillustrated circuit approximately 3 minutes after charging of capacitor59 commences only by lowering the high voltage base of the unijunction.The circuit is designed in this manner to synchronize cut-off of powerafter 3 minutes of operation in synchronism with the derivation of thefirst or master pulse of each data frame; the master pulse is derived onlead 76 in a manner describe infra. To establish synchronism betweenactivation of unijunction 62 and the master pulse, the signal on lead 76is fed to the high voltage base of the unijunction through capacitor 78,whereby the unijunction eta value is reduced, whereby capacitor 59 isdischarged. The negative pulse derived across load resistor 60 is fedvia diode 63 to the base of transistor 46 of latch 42 to energize thelatch and remove bias current from the base of transistor 55. Thereby,transistors 56 and 57 are activated into a cut-off state and power isremoved from the circuits energized through them.

In response to the cut-off of current through transistors 56 and 57reset current is supplied to latch circuit 37 of the sensor stationwhich had previously been activated into an alarm or tripped state. Tothese ends, the emitter of power switching transistor 56 is connectedvia lead 64 to the base of transistor 65 included in electronic resetnetwork 66. While current is being derived from the emitter oftransistor 56, transistor 65 is activated to a conducting state andcapacitor 67, in the collector circuit of transistor 65, is maintainedsubstantially at ground potential. In response to cut-off of current atthe emitter of transistor 56, transistor 65 is cut off and capacitor 67is charged through resistor 68 until the eta value of unijunctiontransistor 69 is reached. In response to the eta value of unijunctiontransistor 69 being achieved, the unijunction is rendered into aconducting state,

whereby transistor 71, connected across load resistor 72 of unijunction69, conducts for a short time interval. Conduction of transistor 71results in a low impedance path being provided between the anode ofdiode 73 and ground, whereby a current path to the input of latch 37 isremoved. If no other current path then exists to the input of latch 37,as occurs only if the detector tapes 31 and 32 of sensor 1 have beenrepaired to tender transistor 33 conducting, the latch is reset.Resetting latch 37 has substantially no effect on the voltage ofcapacitor 36 because it is not connected to any voltage source whiletransistor 33 is conducting, as occurs during periods of no alarm beingdetected, and because of bleed resistor 35. If no alarm is detected bystation 1,

resetting of latch 37 can also be accomplished manually, if no automaticcircuit is provided, by closing normally open-circuited, spring biasedswitch 74. In response to switch 74 being manually depressed, ground ismomentarily established at the base electrode of normally forward biasedtransistor 75 to activate the transistor into a relatively highimpedance state. With the emitter collector path of transistor 75 in arelatively high impedance state, the current supplied to diode 73 isreduced to extinguish latch 37.

To enable 10 data frames, each having a time duration of less than 1second, to be transmitted with a duty cycle of approximately 33 1Spercent, keying levels are sequentially applied by flip-flop 81, withinswitch 14, to transmitter 17. Flip-flop 81 is driven by the output oftiming network 82 which derives sequences of first and second shortduration pulses. The first pulse derived by timing network 82 precedesthe second pulse by approximately 10 seconds, and the second pulseprecedes the next first pulse by approximately 20 seconds. The first andsecond pulses are synchronized with master pulses derived on lead 76,whereby transmitter 17 is keyed on and off at intervals in synchronismwith the master pulses of spaced data frames. To assure repetitiveinitial turn on of the same transistor of flip-flop 81 resistor 501 andcapacitor 502 are connected to the base of transistor 93, wherebytransistor 93 is always initially in an on condition and transistor 94is always initially cut off.

To these ends, timing network 82 includes capacitor 83 that isselectively connected in circuit with resistors 84 and 85 through diodes86 and 87, respectively. Resistors 84 and 85 have differing valueswhich, together with the value of capacitor 83, enable first and secondtime constants of approximately 10 and 20 seconds to be established fortiming network 82. Timing network 82 also includes unijunctiontransistor 88, the high voltage base 89 of which is a.c. coupled viacapacitor 91 to lead 76. In response to the voltage across capacitor 83exceeding a predetermined value while base 89 of unijunction transistor88 is at a relatively low level in response to a frame master pulsebeing derived on lead 76, the unijunction transistor is fired. Firing ofunijunction 88 causes the charge on capacitor 83 to be dissipatedthrough the unijunction so that a negative pulse is developed acrossload resistor 92, connected between capacitor 83 and ground.

The negative pulse developed across load resistor 92 is fed as a triggerto flip-flop 81 to change the conducting state of transistors 93 and 94thereof. In response to transistor 93 being in a conducting state andtransistor 94 being cut off, diode 86 is activated into a conductingstate and diode 87 is cut off, whereby resistor 84 is connected incircuit with capacitor 83. In response to transistor 94 conducting andtransistor 93 being cut off, the opposite conditions exist so thatresistor 85 is connected in circuit with capacitor 83 to the exclusionof resistor 84. Thereby, flip-flop 81 is operated in synchronism withfiring of unijunction transistor 88 and the voltage developed at thecollector of transistor 94 comprises a series of rectangular waveshaving leading and trailing edges displaced from each other byapproximately 10 and seconds and in time synchronism with master pulsesof spaced data frames.

The voltage at the collector of transistor 94 biases the base oftransistor 95 into conducting and nonconducting states. The emittercollector path of transistor 95 is connected between the emitter ofpower switching transistor 56 and a keying input terminal of transmitter17 to energize the transmitter into an active state for approximately 10second intervals synchronized with the occurrence of the first or masterpulse of the first frame in a group of 10 frames and the last pulse ofthe 10th frame of the group. The transmitter remains inactive for 20seconds, until it is again energized into an active conditionsimultaneously with the derivation of the first master pulse of thefirst frame of a succeeding group of frames.

Consideration is now given to the code generator 19 for converting thevalue of precision resistor Slat the sensor station which detected analarm condition. Basically, code generator 19 includes integrator 101, alevel detector 102 and a monostable or one-shot multivibrator 103. Inresponse to the output voltage of integrator 103 reaching apredetermined level, which occurs at a time determined by the slope ofthe integrator output voltage, level detector 102 derives a pulse totrigger monostable 103. Code generator 19 also includes, withinmonostable 103, means for establishing data synchronism between theperipheral and central stations. To these ends, the first or masterpulse of each frame has a longer duration than the remaining pulses ofthe frame, all of which have the same duration. The separation betweenthe leading edges of adjacent pulses is a mark of pulse position. Theseparations are capable of having one of 10 discrete values dependingupon the number of the sensor station detecting an alarm condition andthe identification number of the peripheral station.

Precision resistor 51 of a sensor station detecting an alarm conditionis connected in circuit with integrator 101 for a time interval equal tothe first channel of each frame to determine the r.c. time constant ofthe integrator 101 during that-channel. As seen infra, upon completionof the first channel a different resistor, indicative of a peripheralstation number, is connected to the input of the integrator 101 andremains connected to the integrator only until that channel iscompleted. In this manner, during the different channels differentresistance values are connected in circuit with integrator 101 to enablepulse position data to be derived.

Integrator 101 includes operational amplifier 104 and feedback capacitor105. Capacitor 105 charges at a rate determined by the resistor 51connected in circuit therewith until a predetermined voltage level,determined by the position of the slider of potentiometer 106 and thecharacteristics of Zener diode 107, is reached at the output terminal ofamplifier 104. In response to this voltage level being reached, triggernetwork 108 is activated from its normally nonconducting state into aconducting state to bias the emitter collector path of transistor 109into a low impedance state. The low impedance state of transistor 109 isconnected across capacitor to discharge the capacitor quickly to areference potential, at the input of operational amplifier 104. Inresponse to capacitor 105 being discharged to the reference potential,the output voltage of amplifier 104 suddenly decreases, whereby anegative going pulse is coupled by capacitor 111 to monostablemultivibrator 103. Latch 108 is returned to a nonconducting state almostimmediately after capacitor 105 has been discharged because aninadequate supply of current is fed to the latch through the capacitor.Thereby, the capacitor can again commence to be charged in response tothe voltage applied to the input of integrator 101. Voltage supplied tothe input of integrator 101 is filtered by shunt filter capacitor 112 todecouple sudden changes thereof at the beginning of each channel.Potentiometer 113 is provided in the input circuit of amplifier 104 toprovide a bias drift adjustment; the potentiometer setting can bedifferent for different stations, depending upon differing ambientconditions.

It is to be noted that Zener diode 107 serves a second function ofcontrolling the voltage on lead 76 so that it can never exceed a valuewhere false triggering of sensor stations l-10 can occur in response tomaster pulses at the beginning of each frame. To this end, the cathodeof Zener diode 107 is connected via hold-off diode 1 10 to lead 76.

To enable two different binary one pulse durations to be derived bymonostable multivibrator for master pulse identification, the monostableincludes a switching transistor 114 for selectively varying thepotential applied to charging capacitor 115 of the monostable. The baseof transistor 114 is connected via a d.c. path to lead 76 on which thereis derived a level for enabling detection of which of sensor stations1-10 is in an alarm state; this level is hereafter referred to as asensor code gate and has a duration of one channel. In response to asensor code gate being derived on lead 76 transistor 114 is driven fromits normally cut off condition to a low impedance conducting state sothat monostable multivibrator 103 derives an output pulse or binary onelevel for a relatively long time interval of 34 milliseconds. After the34 millisecond time interval has been completed, monostablemultivibrator changes state whereby a low level, binary zero signal isderived on lead 116. Monostable multivibrator 103 continues to derive abinary zero level until another pulse is fed thereto through capacitor111, at the beginning of the second data channel of a frame. Thereby,the time interval between the beginning of adjacent initial activationsof monostable 103 into a binary one state provide a measure of the valueof the resistor connected to the input of integrator 103 during theperiod between the initial activations.

In response to the pulse fed through capacitor 11 1 at the beginning ofthe second channel, monostable multivibrator 103 is again activated intoa binary one state, whereby a binary one level is derived on lead 116.During the second channel, however, monostable multivibrator 103 remainsin the binary one state for a relatively short duration, such as 17milliseconds, because forward bias is no longer applied to transistor114 to shift the charging level of capacitor 115. Monostablemultivibrator 103 remains in the binary zero state until the third framecommences, as determined by coupling of a pulse through capacitor 111 tothe monostable multivibrator. During the third channel, the monostablemultivibrator 103 again derives a 17 millisecond binary one level, afterwhich it returns to a binary zero level. Monostable multivibrator 103continues to operate in this manner during the fourth and fifth channelsof the frame while peripheral station identification bits are beingapplied thereto. After the fifth channel has been completed, and as thefirst channel of the next succeeding frame begins, monostablemultivibrator 103 is activated into a condition whereby it again derivesa binary one level for a 34 millisecond time interval. These 34millisecond binary one levels derived by monostable multivibrator 103are the master pulses having identifiable characteristics different fromthe other pulses of the frame and enable the central station correctlyto interpret data transmitted thereto from the peripheral stations.

The binary one and zero levels derived on lead 1 16 at the outputterminal of monostable multivibrator 103 are applied to f.m. oscillator22 to control the frequency of the oscillator so that it derives asinusodial output having a first frequency of 1.4 KHZ in response to abinary zero level being generated on lead 116 and a second frequency of1.5 KHz in response to a binary one being derived on lead 116. F.M.oscillator 22 is of the conventional parallel T type and includes afrequency determining network 121 that comprises, interalia, resistor123 and capacitor 124. To vary the impedance of network 121 and therebythe oscillator frequency, resistor 123 is selectively short-circuited bythe source drain path of field effect transistor 125 in response to thebinary signal level derived on lead 116, as coupled to the field effecttransistor through the emitter collector path of switching bipolartransistor 126. Since the remaining circuitry of oscillator 22 isconventional, no detailed description thereof is provided. The outputtones of oscillator 22 are fed to amplitude modulator 23, as describedsupra in conjunction with FIG. 1.

To control the sequential readout of the first channel of each frame(the channel that indicates which of the sensor stations is detecting analarm condition) and the second through fifth channels of each frame(the channels that designate the identification number of the peripheralstation in four decimal decades), output signals of monostablemultivibrator l 16 are coupled via capacitor 131 and transistor 132 todivide by five counter 133. Counter 133 includes three binary stages134, 135 and 136 interconnected with each other in a well known mannerso that five different combinations of outputs are derived from the twooutput leads of each of stages 136-138.

Because counter 133 includes three stages it can be initially activatedto any one of eight different states, termed unallowable states. In theevent of counter 133 being initially activated to one of the unallowablestates the counter is returned to its initial state in response to thefirst input pulse fed thereto after application of power. To this end,the voltage at output terminal 141 of stage 138 has a binary one levelonly if counter 133 is in an unallowable state. This binary one level isfed back to the input of transistor 142 of stage 136 via couplingresistor 143 and causes the first pulse applied to the input of counter133 to derive the counter to its initial condition.

Counter 133 supplies pulses in sequence to its output terminals 141 and144-148 in response to the successive application of input pulsesthereto from monostable multivibrator 103 to enable resistors indicativeof the identification number of the peripheral station and the sensorstation detecting an alarm condition to be connected in sequence to theinput of integrator 101. To establish identification codes for up to9999 different peripheral stations, identification number generator 21includes four different precision resistors 151-154. Each of resistors151-154 can have any one of 10 discrete values to determine the numberof identification code for a particular peripheral station. Thereby, thecombination of precision resistors 151-154 at each of the peripheralstations is different to establish different pulse positionidentification signals.

Precision resistors 151-154, as well as the precision resistor 151 ofthe sensor station detecting an alarm condition, are sequentiallyconnected in circuit with the input of integrator 101 in response to thesequential derivation of binary zero and one levels at terminals 141 and144-148 of counter 133. Conducting paths to the input of integrator 103through precision resistors 151-154 are respectively provided by theemitter collector paths of normally cut off switching transistors161-164. The conducting states of transistors 161-164 are respectivelycontrolled by the collector voltages of normally conducting transistors171-174, the bases of which are connected to be responsive to thevoltages at terminals 141 and 144-148 through resistor decoding network175. Three decoding resistors 176 of network are connected betweenoutput terminals of the three counter stages 136-138, whereby only oneof transistors 171-174 can be activated into a cut-off condition at atime. The selected one of transistors 171-174 that is driven into cutoff causes the base voltage of the switching transistor 161-164 withwhich it is connected to be forward biased whereby a path for thecorresponding one of resistors 151-154 is provided between ground andthe input of integrator 101.

In the event of counter 133 being initially in an unallowable state,identification number generator 21 is energized so that resistor 151 isinitially connected in circuit with the input of integrator 101, wherebyan output signal can be derived from a monostable multivibrator 103 toenable further triggering of counter 133. To this end, there is provideda normally conducting transistor 177, the base of which is connected toterminals 146 and 148 of counter 133. If counter 133 is initially in anyof the unallowable states, terminals 146 and 148 feed bias voltages tothe base of transistor 177 through resistors 178 to cut off transistor177. The collector of transistor 177 is connected via resistor 179 tothe base of transistor 161, whereby the emitter collector path oftransistor 161 is activated to a closed state as long as counter 133remains in the unallowable state.

This assures the derivation of an output pulse from monostablemultivibrator 103 and drives counter 133 back to its initial condition.

To enable transistor 52 of the sensor station detecting an alarmcondition in sequence with energization of transistors 161-164,transistor 181 is provided. Transistor 181 is connected via resistors182, which can be considered as part of decoding network 175, toselected ones of terminals 141 and 144-148 in such a manner thattransistor 181 is driven from its normally conducting state into acut-off condition in response to resistor 154 being decoupled from theinput of integrator 101. The collector of transistor 181 is connected tolead 76 which feeds sensor code gates to timing circuit and switch 14and to control the conduction of transistor 114 of monostablemultivibrator 103, as described supra. The collector of transistor 181also connected to the base of transistor 52 to drive the emittercollector path of transistor 52 of the sensor station detecting an alarmcondition into a conducting state, whereby precision resistor 51 at thesensor station is connected to the input of integrator 101.

A further feature of the invention concerns a network for monitoringsensor stations 1-10 and providing a visual indication to personnel atthe guarded premises of one of the sensor stations being in an alarmcondition or none of the sensor stations being in an alarm condition.Tothis end, red and green indicator lamps 185 and 186 are provided.Indicator lamp 185 is energiz'ed in response to an alarm condition beingdetected by any one of sensor stations l-l0, while lamp 186 is energizedin response to none of the sensor stations detecting an alarm condition.Indicator lamps 185 and 186 are, in effect, responsive to the voltage atthe emitter of transistor 38 of latch circuit 37.

In response to an alarm condition being detected, the emitter oftransistor 38 is substantially at ground potential, which is coupledthrough diode 73 to the emitter of transistor 75 to activate the lattertransistor into a conducting state. In response to transistor 75 beingactivated into a conducting state, transistor 188 is forward biased sothat the collector thereof supplies positive current to the base oftransistor 187. Transistor 187 is thereby activated into a conductingstate and lamp 185 is energized. Simultaneously with transistor 187being activated into a conducting state, transistor 189, the base ofwhich is do. coupled to the collector of transistor 187, is renderedinto a cut-off condition. With transistor 189 cut off, diode 190,connected to the collector thereof and to indicator lamp 186, is backbiased. Back biasing of diode 190 prevents the flow of current toindicator lamp 186 and it is not activated as a result. In response tolatch circuit 37 being in a nonconducting state, a relatively highvoltage is applied to the emitter of transistor 75,whereby theconducting properties of transistors 187-189 are reversed and lamp 186is energized to the exclusion of lamp 185.

The system of FIGS. 2a and 2b responds to the value of precisionresistor 51 at a sensor station responding to an alarm condition and thevalues of code identification precision resistors 151-154 to derive aplurality of frames, having a wavetrain as indicated in FIG. 3a. FromFIG. 3a, it is noted that the first binary one level or bit within eachframe has a length, t considerably in excess of the other binary bitswithin the frame, which bits have a duration of t The time intervalsT,-T between the leading edges of the adjacent pulses within the dataframe respectively define the magnitude of the 10 discrete levelsassociated with which'one of the sensor stations 1-10 detects an alarmand the three'most significant decades of the station identificationnumber. The time interval, T between the leading edge of the fifth pulsein each frame and the leading edge of the first or master pulse of thenext succeeding frame has one of 10 discrete levels indicative of theleast significant decade of the peripheral station identificationnumber. The timeintervals T -T define five different channels within aframe and are frequently referred to herein as such.

Data frames transmitted from different peripheral stations or from thesame peripheral station in response to different sensor stationsdetecting an alarm condition have different frame durations whereby theframe rate can be considered essentially as random for any particular,peripheral station or sensor station. The random nature of frameduration occurs because of the pulse position modulation techniquewhereby the spacing between adjacent pulses can be different and becausethe fifth channel of each frame is completely occupied by data, themagnitude of the least significant decade of the peripheral station codenumber. Since the last channel of each frame is followed immediately bya master pulse of the next succeeding frame, there are no unusual timesegments and the highest data transmission rate possible can beemployed.

The wavetrain illustrated by FIG. 3a is transmitted to the centralstation, the block diagram of which is disclosed in FIG. 4. The centralstation includes an omnidirectional antenna 201 which feeds receiver 202that is tuned to the frequency of transmitter 17 of each peripheralstation. Receiver 202 demodulates the amplitude modulated signaltransduced by antenna 201 and feeds a series of tones having a frequencyof 1.4 KI-Iz or 1.5 KHz to tone detector 203. Tone detector 203 derivesbinary one and zero levels that are fed to data line 204 and arereplicas of binary levels derived by code generator 19, FIG. 2b. Tonedecoder 203 also drives pulse width discriminator 205 which includes apair of output leads 206 and 207.

Discriminator 205 responds to the length of the tones derived by decoder203 to derive, on lead 206, a binary one level in response to a binaryone signal being derived by the tone decoder for a predetermined timeinterval slightly less than the time interval t of the second throughfifth pulses of each frame; in an exemplary embodiment, pulse widthdiscriminator 205 derives a binary one level on lead 206 in response toa binary one being derived by tone decoder 203 for an interval in excessof 12 milliseconds. Discriminator 205 also includes circuitry forderiving a binary one on lead 207 in response to tone decoder 203deriving a binary one level for a time interval slightly less than thelength, t of the master or first pulse of each frame; in the exemplaryembodiment, discriminator 205 derives a binary one signal on lead 207 inresponse to decoder 203 generating a binary one level for in excess of30 milliseconds. The wavetrains derived on leads 206 and 207 arerespectively illustrated in FIGS. 3b and 3c. Discriminator 205 feedsbinary one signals to leads 206 and 207 for a predetermined timeinterval after the minimum elapsed detection-times of 12 and 30milliseconds. The lengths and occurrence times of the pulses derived onleads 206 and 207 are such that the trailing edges of pulses on lead 206occur after the trailing edge of the longest data pulse transmitted froma peripheral station and the trailing edges of pulses on lead 207 occurafter the trailing edge of the pulses on lead 206.

The output signals of pulse width discriminator 205 on leads 206and 207are combined in logic network 208 to enable the master pulse within eachframe to be detected. Logic network 208, the details of which aredescribed infra, derives a binary one level on load output 209 thereofin response to a master pulse being detected simultaneously with a loadenable signal being supplied to logic network 208 on lead 211. Asdescribed infra, the signal derived on lead 211 is generated by shiftregister 212, which is responsive to the load indicating signal on lead209, as well as shift and reset signals, respectively, derived by logicnetwork 208 on leads 213 and 214.

Logic network 208 responds to binary one levels on data lead 204 toderive shift pulses on lead 213, as indicated by the waveform of FIG.3d. The trailing edge of each shift pulse, regardless of the channelnumber within a particular frame, always occurs a predetermined timeinterval after the leading edge of the data pulses derived on lead 204,as indicated by FIG. 3a. The shift pulses for the second through fifthchannels of each frame have leading edges displaced by the same timeinterval from the leading edges of the corresponding channel pulsesderived on data line 204, as indicated in FIG. 30. It is also to benoted that each of the shift pulses for the second through fifthchannels of each frame has substantially the same duration. The timedisplacement and duration of the shift pulses for the second throughfifth frames are identical because the apparatus in logic network 208for deriving them is thesame. The shift pulse, however, for the firstchannel of each frame is displaced from-the leading edge of the datapulse for the first frame by a greater interval than the separationbetween the leading edges of the data and shift pulses for the secondthrough fifth frames. This is to enable certain operations relating todetection of a master pulse to occur in logic network 208, as well as toenable other operations in other circuit elements of the central stationto be performed prior to the derivation of the fist shift pulse of eachframe. In the event of a long, greater than 38 milliseconds; noise pulsebeing received, logic circuit 208 includes means for preventingderivation of a shift pulse.

The reset pulse derived on lead 214 by logic network 208 is derived inresponse to a master pulse not occuring within a predetermined timeinterval, slightly more than the maximum l-second duration of a frame.In response to such a condition, it can be assumed that datatransmission between a peripheral station and the central station hasterminated, necessitating activating the decoding equipment of thecentral station to an initial state. A reset pulse is also derived inresponse to other conditionsassociated with a lack of synchronizationbetween received data and the operation of the central station, asdescribed infra.

Shift register 212 includes five cascaded binary or flip-flop elementswhich are activated .to a binary one state in sequence and synchronouslywith the trailing edges of the data shift pulses on lead 204, FIG. 3d.The trailing edges of the shift pulses activate'the cascaded five stagesof shift register 212 so that only one stage is activated at a time foraduration between trailing edges of adjacent shift pulses. The separateand sequential activation of the five cascaded stages of shift register212 for stages 1, 2 and 5, which correspond with channels 1, 2 and 5,respectively, is illustrated by the rectangular waveforms of FIGS. 3e,3f and 33. The waveforms of FIGS. 3e, 3f and 3g represent binary levelsderived by the first, second and fifth stages of the five cascaded stageshift register; the output signals of the first through fifth stages ofthe cascaded-shift register are derived on leads 221-225, respectively.

If none of the stages of the cascaded shift register is in a binary onestate or with the fifth stage of the register activated to a binary onestate, as indicated by the time interval T (FIG. 3g), a load enablesignal is derived on lead 211. From an inspection of FIGS. 3d and 33,the load enable signal has a binary one level in time coincidence withat least a portion of the binary one level derived on shift lead2l3in'response to reception of the master pulse for the next succeedingframe. Thereby, the first stage of the five cascaded stages is loadedwith a binary one signal in synchronism with a shift pulse being appliedto the shift register via shift lead 213 and the first stage of theshift register is activated to a binary one state.

Shift register 212, in addition to being provided with five cascadedstages, includes an additional stage which is partially decoupled fromthe five cascaded stages. The additional stage is responsive to thesignals on leads 209, 213, and 214 in such a manner that it is activatedto a first state upon the completion of the first channel of one frameand remains in that state until the first channel of the next succeedingframe has been completed. The additional stage is then activated for oneframe into a second state for a corresponding time interval of the nextsucceeding frame. The resulting, complementary output signals of theadditional stage of shift register 212 are fed to the shift registeroutput leads 226 and 227, respectively.

To monitor the time interval each of the stages of the five cascadedstage register in shift register 212 is ac-- tivated to a binary onestate, and an array of counters and storage elements is provided innetwork 231. Network 231 includes six different decade counters drivenat different time intervals in response to pulses derived from 42 Hertzsynchronized clock 232. Clock 232 is synchronized by the trailing edgeof each shift pulse derived on lead 213 so that it derives a clock pulsein time coincidence with the trailing edge of each shift pulse. Thereby,during each channel of a frame, clock source 232 is resynchronized sothat the number of pulses derived during the length of each channel is ameasure of the channel duration.

The six counters within network 231 respond to the clock pulses ofsource 232 at different time periods controlled by the rectangular wavevoltages on leads 221-227. Two of the counters within network231 areresponsive to binary one levels on leads 221, 226, and 227 while theremaining four counters are separately responsive to the binary onelevels on leads 222-225. In response to the signals on leads 222-225,each of the four remaining counters is activated once during each framefor time intervals coextensive with the duration of each channel.Thereby, upon completion of each data frame, each of the four remainingcounters stores a decimal number signal indicative of the identificationcode number of the four significant decades of each peripheral station.

The first and second counters within network 231 are alternatelyactivated during the first channel of successive frames into a statewhere they are responsive to clock pulses from source 232. The alternateactivation of these two counters within network 231 results from thesignals applied to the counters by leads 221, 226 and 227. Thealternately activated counters store decimal number signals indicativeof which sensor station at the peripheral station detects an alarmcondition. It is necessary to employ alternately activated counters fordifferent data frames because the last channel of a first frame isfollowed immediately by the first channel of the next succeeding frame,necessitating alternate readout of the contents of the first and secondcounters into a storage register during the first channel-of alternateframes. The counters employed cannot operate properly if read out whilebeing loaded.

Network 231 is provided with five storage registers, four of which areresponsive to the decade counters for channels two through five. Theremaining storage register of network 2131 is sequentially responsive tothe two alternately activated counters. Thereby, one of the countersfeeds the remaining storage stage in response to one data frame beingcoupled into the storage registers and the other counter feeds theregister in response to the next succeeding data frame being read out.

To control readout of the counters in network 231 to the registers ofthe network, logic network 208 includes a data strobe output lead 233 onwhich is derived a relatively short duration pulse, illustrated in FIG.3i. The data strobe pulse is derived immediately after termination ofthe trailing edge of the shift pulse for the first channel of eachframe. Thereby, data are transferred from the counters to the registersof network 231 during the first channel of each data frame.

Immediately after a data strobe pulse is derived on lead 233, logicnetwork 208 derives a counter reset pulse on lead 234, indicated by thewaveform of FIG. 3j. Each counter reset pulse resets the contents of thefour counters in network 231 responsive to the signals on leads 222-225and one of the two counters responsive to the channel one signal on lead221. The Channel one counter which is reset is the one which has justbeen read out and the other counter is at that time activated into astate whereby it is responsive to the clock pulses of source 232. Duringthe first channel of the next frame the operations of the two channelone counters are reversed.

The five registers of network 231 thereby continuously store signalsindicative of the discrete values of the five different channels of eachframe. The signals stored in the registers are continuously updated inresponse to each frame read from the counters in response to the datastrobe pulse on lead 233. Each of the signals stored in the fiveregisters of network 231 is converted into a four-bit binary codeddecimal signal that is continuously fed from the registers to a bank ofindicator lamps 235 and a printer 236. Easily read numerical indicationsof the identification codes of the transmitting peripheral station andthe sensor station at the peripheral station detecting an alarm areprovided by indicator 235. Printer 236 responds periodically to thesignals in the registers at a relatively high rate on the order of threeframes a second to provide a continuous, repetitive hard copy readout ofthe indications of station identification and sensor station detectingan alarm condition. The repetitive readout by printer 236 provides ahigh degree of integrity to the system since a system operator can beassured of the identity and cause of an alarm by the repetitive printeddata readout. Indicator 235 can also be provided with an audio alarmwhich is sounded in response to several data frames being coupledthereto.

One additional feature of the present invention concerns the ability totest the frequency of clock pulse source 232. To this end, test gategenerator 237 for deriving a binary one level for a relatively long timeperiod, of for example 1 second, is supplied to counters of network 231to enable the counters to be responsive to pulses from clock source 232.While the test generator binary one signal is supplied to the counters,the counters are connected in a cascaded arrangement, whereby a carrysignal is derived from a lower order counter and is supplied to a higherorder counter. After the l-second interval has been completed, the countof the several counter stages should have a predetermined value, whichis read out by indicator 235. If indicators 235 do not have anappropriate value, an indication is provided to an operator that thereis either a malfunction in the counter network'or clock 232 is notoperating at its preassigned frequency.

Having described the block diagram of the central station and the basicoperations occurring at the central station, consideration will now begiven to the circuits included in pulse width discriminator 205, logicnetwork 208, shift register 212, and network 231 by referring to thecircuit diagram of FIGS. 5 and 6. The circuits of FIGS. 5 and 6 includeNOR and NAND gates; in certain instances, a single input is applied toone of the NOR gates or plural inputs of one of the NOR gates areresponsive to the same signal, in which cases the NOR gates function asinverters. In certain instances, all of the inputs of a NAND gate areresponsive to a source source, whereby NAND gates so connected functionas inverters. The circuits of FIGS. 5 and 6 also include a multiplicityof integrated circuit J-K flip-flops which include trigger or toggleinput terminals, J and K input terminals that function in conjunctionwith the toggle input terminals, as well as set and reset inputterminals that are independent of the toggle input terminal. The .I-Kflip-flops include binary output terminals, denominated as Q and O. Thecircuits of FIGS. 5 and 6 also include a number of integrated circuitoneshot multivibrators for deriving output signals of predeterminedamplitude and width in response to a trigger voltage being appliedthereto. Integrated circuit decade counters and registers for derivingfour-bit binary coded decimal signals are also provided in the circuitsof FIGS. 5 and 6.

Considering FIG. 5 in detail, binary one and zero levels derived fromtone decoder 203, as illustrated in FIG. 3a, are fed by lead 251 topulse width discriminator 205 through inverter 252. The output signal ofinvertor 252 is applied in parallel to timing networks 253 and 254,which are identical to each other except with regard to the value of aresistance capacitance timing circuit included in each, whereby adescription of network 253 suffices for both timing networks.

Timing network 253 derives a short duration binary one pulse in responseto a binary one of the data wavetrain occurring for greater than a timeinterval of 12 milliseconds. To this end, timing circuit 253 includes anormally conducting NPN transistor 255, having a base electrodeconnected to the output of inverter 252. The collector of transistor 255is connected in shunt with timing capacitor 256 that is connected inseries circuit with a dc. voltage via resistors 257. The voltage acrosscapacitor 256 is monitored by unijunction transistor 258, the lowvoltage base of which is connected to ground through load resistor 259.In the absence of a binary one in the data wavetrain on lead 251, thecollector of transistor 255 substantially short circuits capacitor 256to ground. In response to a binary one level on lead 251, the base biasof transistors 255 decreases to cut off transistor 255, thereby allowingcapacitor 256 to be charged through resistors 257. With transistor 255in a nonconducting state for a predetermined time interval, of at least12 milliseconds and capacitor 256 is chanrged through resistors 257until the threshold voltage of unijunction transistor 258 is reached andthe unijunction is fired to discharge capacitor 256 through loadresistor 259. The threshold level of unijunction transistor 258 and themagnitude of the time constant of the r.c. circuit comprising capacitor256 and resistors 257 are such that a relatively short duration pulse isderived across load resistor 259 after a binary one level is derived ondata input lead 251 for 12 milliseconds. Timing circuit 254 is similarlyarranged, except that the r.c. time constant of resistors 261 andcapacitor 262 is adjusted to provide a relatively short duration pulseacross load resistor 263 in response to a binary one level being on datainput lead 251 for a time period in excess of 30 milliseconds.

The short duration output pulses of timing circuits 253 and 254 arerespectively fed to the bases of transistor inverters 264 and 265.Transistors 264 and 265 respond to the short duration pulses appliedthereto by timing circuits 253 and 254 to feed triggering voltages intointegrated circuit one-shot multivibrators 266 and 267. One-shotmultivibrators 266 and 267 are provided with timing capacitor 268 andvariable resistor 269 to determine the durations of binary one statesderived thereby, as indicated by FIGS. 3b and 3c. The state of one-shotmultivibrator 266 is monitored on complementary output lead 271 thereof,while the state of one-shot 267 is monitored on true and complementaryleads 272 and 273.

From FIG. 3b it is seen that one-shot multivibrator 266 is activatedinto a binary one state at a predetermine time interval, 12milliseconds, after the derivation of each binary one level in the datasignal on lead 251, as represented by FIG. 30. An inspection of FIG. 3creveals that the output of one-shot multivibrator 267 on lead 272 is insynchronism with the master or first pulse of each frame and occurs apredetermined time interval, 30 milliseconds, after the leading edge ofthe master pulse of the frame. The lengths of the pulses of FIGS. 3b and30, which pulses are occasionally denominated as Q and 0,, respectively,are adjusted such that Q, slightly overlaps the widest data pulse and Qslightly overlaps Q The reset pulse on lead 214, FIG. 4, is derived,inter alia, in response to no master pulse having been received for atime interval in excess of 1 second, the maximum duration of any frame.To this end, the signal on lead 272 is applied to a further timingnetwork 275, which is substantially identical to timing networks 253 and254, except that the r.c. time constant of resistors 276 and capacitor277 is slightly in excess of 1 second. Thereby, a pulse is derivedacross load resistor 278 only in response to the output of one-shotmultivibrator 267 on lead 272 having a binary zero level for a timeperiod greater than 1 second. This signifies the failure of a masterpulse to occur for slightly more than a 1- second interval and signaltermination of data transmission from the peripheral station to thecentral station. The reset pulse generated across load resistor 278 isutilized in a manner described infra.

To derive shift pulses on lead 213 for each channel of each frame, theoutput of inverter 252 and the complementary output one-shotmultivibrator 266 on lead 271 are combined in NAND gate 281, having anoutput which is phase reversed by inverter 282. The shift output signalof inverter 282, FIG. 3d, is thereby at a binary one level only inresponse to one-shot 266 being in a one state while the data inputsignal, FIG. 3a, has a binary zero value. Thereby, the trailing edges ofthe shift wavetrain, FIG. 3d, are in time coincidence with the trailingedges of the changes in the state of one-shot 266, as illustrated inFIG. 3b. Since the trailing edges of changes in the state of one shot266 always occur a predetermined time period after the leading edges ofthe channel data pulses, FIG. 3a, the separations between trailing edgesof adjacent shift pulses enable channel duration to be monitored.

One feature of the logic network for deriving the shift pulses is that ashift pulse is not derived if a noise pulse having a length considerablygreater than 34 milliseconds is received at the central station. This isbecause of the phases of the signals applied to NAND gate 281 and theinherent gate characteristics.

Consideration is now given to shift register 212 that includes fivecascaded J-K flip-flops 283487, one being provided for each of the fivedifferent channels of each frame. Flip-flops 283287 are designed to beactivated so that flip-flop 283 is in a binary one state while the firstchannel of each frame is being processed; flip-flop 284 is to beactivated into a binary one state while the second channel of each frameis being processed and so forth for flip-flops 285-287 visa-vis channelsthree-five.

To these ends, the shift output signal of inverter 282 is applied inparallel to the toggle input 291 of each of flip-flops 283-287. The Qand 6 output terminals of the cascaded flip-flops 283-286 arerespectively connected to the J and K input terminals of flip-flops284-287 to establish the cascaded shift register configuration. Outputsignals are derived from flip-flops 284-287, as indicated by thewaveforms of FIGS. 3e-3g at the Q output terminals of the flip-flops.

To control loading into the first shift register stage, flip-flop 283,the complementary output of one-shot 267, on lead 273, is fed in acomplementary manner to the J and K input terminals of flip-flop 283 viaserially connected NOR gate 288 and inverter 289, the outputs of whichare respectively connected to the J and K input terminals of flip-flop283. NOR gate 288 is also responsive to the output of NAND gate 292which signals if none of stages 283-287 is in a one state or if onlystage 287 is in a one state since it is responsive to the Q outputs offlip-flops 283-287. There is no need and it is undesirable to connectflip-flop 283 to NAND gate 292 because of the time relationship betweenthe inputs thereof during loading. The J and K inputs of flip-flop 283are thereby respectively provided with binary one and zero input levelsin response to monostable 267 being in a one state while a binary zerois derived from gate 292 which signifies that a master pulse is beingreceived while flip-flop 287 is in the one state (propersynchronization) or while none of flipflops 283-287 is in the one state,as can occasionally occur due to improper synchronization. Flip-flop 283is loaded with the signals applied to its J and K input terminals onlyin response to the trailing edge of a shift pulse derived by inverter282 being fed to its toggle input terminal 291. As indicated by FIGS.3d-3e, flipflop 283 is therefore activated into a binary one state forthe interval between the trailing edge of the relatively narrow firstshift pulse of each frame and the trailing edge of the second shiftpulse of each frame.

While flip-flop 283 is in a binary one state during the interval T FIG.3e, enable voltages are applied by the Q and 6 outputs thereof to the Jand K input terminals of flip-flop 284. Flip-flop 284 is not activatedinto a binary one state, however, until the occurrence of the trailingedge of the next or second pulse of each frame derived by inverter 282.In this manner, flip-flops 285-287 are energized in sequence for thethird through fifth channels of each frame. Activation of shift registerstages 283-287 into a binary one state is always a predetermined timeafter the leading edge of the corresponding pulse for each channel isderived on data input lead 251. Thereby, the time duration each ofstages 283-287 as maintained in a binary one state serves is a measureof the five channel times of each frame. It is also to be noted that theidentifiable characteristic of the master pulse, its relatively widewidth of 34 milliseconds, enables proper synchronization betweenactivation of stages 283-287 and the received data channels.

To control the two counters in network 231, FIG. 4, for the firstchannel of each frame, shift register 212 is provided with an additionalJ-K flip-flop 294 that includes a toggle input 295 driven in parallelwith toggle inputs 291. Flip-flop 294 is activated so that it stays in afirst state for one data frame and is switched to stay in a second statefor the next succeeding data frame received at the central station.Activation of flip-flop 294 into its different states is simultaneouswith activation of flip-flop 284 into its different statessince the Jand K input terminals of flip-flop 294 are connected to be driven inparallel by the signal derived at the Q output terminal of flip-flop283. Thereby, flip-flop 294 functions effectively as a toggle that isactivated every other time flip-flop 283 changes state, in response tothe trailing edge of the Q output of flip-flop 283.

In the event of an interruption of transmission between the peripheralstation and the central station, it is necessary to reset flip-flops283-287 and 294 so that each has a zero state and flip-flop 283 can beloaded to a binary one state in response to reception of the next masterpulse. To derive a reset input for flipflops 283-287 and 294, the outputsignal of timing circuit 275 is reversed in phase by inverter 296, theoutput of which is combined with output signals of NAND gate 292 and thetrue output of monostable multivibrator 267 on lead 272. The signal onlead 272 and the output signal of NAND gate 292 are combined in NANDgate 297, the output terminal of which is connected to an input of NANDgate 298, having a second input responsive to the output of inverter296. The output of NAND gate 298 is invertedin phase by inverter 299,which derives an output signal that is applied in parallel to the resetinput terminal of each of flip-flops 283-287 and 294. The set inputterminals of flip-flops 283-287 and 294 are connected to a dc. powersupply voltage which prevents activation of the flip-flops to the setstate. The interconnections between the output signals of multivibrator267, NAND gate 292 and timing network 275 with logic gates 296-299 aresuch that a reset pulse is applied by inverter 299 to flip-flops 283-287and 294 in response to a pulse being derived from timing circuit 275 ormonostable 267 being in a binary one state while any one of flip-flops284-286 is in a binary one state. These conditions can occur in responseto cessation of transmission between the peripheral and central stationfor a period in excess of I second, the maximum time duration of a dataframe, or if a master pulse is being processed while the shift registerhas a binary one value in any of stages two, three or four, anindication of lack of synchronization between received data channels andthe operation of the central station.

To control synchronization of clock source 232, the trailing edges ofshift pulses derived at the output of inverter 282 are fed to the inputof oscillator 232 via leads 301. As described infra, the synchronizedclock pulses derived by source 232 are fed to counters in network 231.

To derive the end of frame, data strobe and counter reset signals ofFIGS. 3h, 31' and 3j, respectively,-shift register 212 includes an endof frame logic network 311. End of frame logic network 311, illustratedin FIG. 5, includes J-K flip-flop 312, having J and K input terminalsdriven by complementary signals. The signal supplied to the J inputterminal of flip-flop 312 is derived by NOR gate 313 in response to thecomplementary output of monostable multivibrator 267 on lead 273 and thecomplementary, 6, output of flip-flop 287 for the fifth channel. Theoutput of NOR gate 313 is applied directly to the J input terminal offlip-flop 312 and is applied in inverted form via inverter 314 to the Kinput terminal of the flip-flop. The toggle input terminal 315 offlip-flop 312 is responsive to the trailing edge of output signalsderived by inverter 282. The set and reset input terminals of flip-flop312 are driven in parallel with the corresponding terminals of flipflops283-287. Thereby, the Q output terminal of flipflop 312 is a rectangularwaveform illustrated in FIG. 3h. The waveform of FIG. 3h has a binaryzero level until a frame has been completed, at which time a binary onelevel is derived in synchronism with the trailing edge of the shiftpulse for the first channel of the next succeeding frame.

The Q output terminal of flip-flop 312 is combined with the true outputof monostable 267 on lead 272 in NAND gate 316. The output signal ofNAND gate 316 is thereby a relatively short duration pulse having aleading edge in time coincidence with the leading edge of each end offrame pulse, illustrated by FIG. 3h. The trailing edge of each datastrobe pulse is in time coincidence with the trailing edges of thebinary one levels derived on lead 272, FIG. 30, if these binary onelevels are in time coincidence with a portion of the end of framewavetrain. The counter reset signal is derived by sensing the trailingedge of the data strobe pulse derived at the output terminal of NANDgate 316. To this end, differentiator 317, including circuitry forresponding only to the trailing edge of the output of NAND gate 316, isprovided. The output waveform of differentiator 317 is illustrated inFIG. 3

The various output signals of FIG. 5, derived, inter alia, from the Qoutput terminals of flip-flops 283-287 and 294, the Q output offlip-flop 294, the data strobe output of NAND gate 316, the outputsignal of differentiator 317, and the output signal of synchronizedclock source 232 are combined in the counter and register circuitryspecifically illustrated in FIG. 6 to enable indications of the discretelevels of the values of each channel to be measured and displayed. Thenetwork of FIG. 6 includes six integrated circuit decade counters 321,321 and 322-325. Counters 321 and 321 are identical, each being providedwitha count input, denominated as a, as well as a pair of reset to zeroinputs R and R Counters 321 and 321' are reset to zero only in responseto binary one signals being simultaneously applied to the two resetinputs. Counters 321 and 321' also include an external connectionbetween the least significant output bit thereof, A, and an inputterminal b,, to establish the binary decimal counting configuration. Inaddition to the A output ter minal, each of the counters is providedwith three other binary outputs to enable the 10 different decade statesto be defined. Counters 322-325 are essentially identical to counters321 and 321, except that the former counters are reset to a zero statein response to a binary one being fed only to the R input terminalthereof.

Counters 322-325 are employed to measure the duration of the secondthrough fifth channels of each frame and to this end are activated to beresponsive to the output of sync data clock 232 and to voltagesdeveloped at the Q output terminals of flip-flops 284-287. Signals arecoupled to the a or count input terminals of counters 322-325 inresponse to binary ones being derived at the Q output terminals offlipflops 284-287 by combining the flip-flop output signals with theoutput of data clock 232 in logic networks 332-335, one of which isprovided for each of the counters 322-325. Since each of the logic gates332-335 is essentially the same, a description of network 332 sufficesfor the remaining networks, except for one aspect of network 335.

Logic network 332 includes NAND gate 336, having one input responsive tothe signal derived at the Q output terminal of flip-flop 284 and asecond input responsive to the clock signal derived by synchronized dataclock source 232. The output of NAND gate 336 is fed as one input toNAND gate 337, the output of which drives the count input of counter322, at input terminal a. In response to each pulse derived by dataclock source 232 while a binary one is being derived at the Q outputterminal of flip-flop 284, a pulse from clock source 232 is supplied tocounter 322 and the state of the counter is advanced in responsethereto. By selecting the clock rate of source 232 appropriately, thecount stored in counter 322 after the termination of a channelcorresponds with the discrete decade level of the peripheral stationidentification code for the most significant decade number of the code.Each of counters 323-325 is similarly activated whereby, upon completionof a data frame, these counters store decimal numbers corresponding withthe three lower decades of the peripheral station code identificationnumber.

Logic network 332 includes an additional NAND gate 338 having one inputresponsive to l-second test gate generator 237 to enable the frequencyof clock source 232 and the proper functioning of the counters to beascertained. Test gate source 237 activates NAND gate 338 into anenabled condition for a period of I second while pulses are beingderived by source 232 in a continuous manner unrelated to the occurrenceof any master pulse.

While the test operation is being performed, counters 322-325 arecascaded together so that the most significant bit output terminal ofone counter is fed to the count input of the next adjacent counter. Tothis end, a second input terminal of NAND gate 338 is responsive to themost significant bit output of counter 232, at terminal D. The outputterminal of NAND gate 338 is supplied as a second input to NAND gate337, whereby counter 322 can be supplied with pulses from terminal D ofcounter 323 while the l-second test gate is being derived. Logic network335 differs from logic network 332 slightly in this regard since NANDgate 339 of network 335 cannot be connected to the most significant bitoutput terminal of a preceding decade counter. Therefore, the inputterminal of NAND gate 339 corresponding with the input terminals of NANDgate 338 is directly responsive to the output of clock source 232. Allpulses from clock source 232 propagate to the a input terminal ofcounter 325 while test gate source 237 is activated. After a count of 10has been reached in counter 235, the output signal derived at the Doutput terminal thereof is propagated to the count input terminal ofcounter 325, which will not receive a. further input pulse until 10additional pulses are fed to the a input terminal of counter 325. In themanner described, it is believed evident as to the manner by whichcounters 322-325 are responsive to the output of clock source 232 whilea test gate signal is being generated.

Counters 321 and 321 measure the duration of the first channel ofalternate data frames, whereby counter 321 provides a readout of, forexample, the duration of the first channels of frames 1, 3, 5, etc.,while counter 321 provides a readout of the first channel of frames 2,4, 6, etc. To effect control of first channel counters 321 and 321 inthis manner, the signal at the Q output ter minal of flip-flop 283 iscombined in a logic network comprising NOR gates 341 and 342 with theoutput signals at the Q and Q output terminals of flip-flop 294

1. A system for transmitting to a central station an indication of theexistence, at any one of a plurality of peripheral stations, of any oneof several possible alarm conditions, comprising, in combination, meansfor deriving a signal in response to the occurrence of any one of saidconditions, frame generating means responsive to said signal forgenerating a predetermined plurality of repetitive sequentialsubstantially identical data frames, said frame generating meansincluding data channel producing means for producing a plurality ofrepetitive data channels each enduring for a discrete multiple of apredetermined unit time elapse, said data channels being respectivelyindicative of the identity of said peripheral station and the conditionat said peripheral station; said frame generating means including meansfor providing a distinguishable timing signal characteristic of thefirst channel of each frame to distinguish same from other channels ofeach frame, and means for transmitting said predetermined plurality ofdata frames to said central station, wherein is provided means to assurethat the last of said plurality of frames terminates in saiddistinguishable timing signal characteristic and the first of each ofsaid channels commences with said distinguishable timing signalcharacteristic.
 2. A system according to claim 1, wherein said each ofsaid peripheral stations includes a normally disabled radio wavetransmitter, control means responsive only to the initiation of one ofsaid conditions for conditioning said transmitter to transmit a radiowave for only a predetermined time interval, and modulating means formodulating said radio wave according to the time durations of saidchannels and the identifiable timing signal characteristics of saidchannel of each of said repetitive data frames and means for terminatingsaid predetermined time interval only co-incidentally with terminationof one of said frames.
 3. A peripheral station according to claim 2,wherein said control means includes means for periodically enabling saidtransmitter to an on condition for groups of said frames separatedrespectively by blank intervals of about twice the duration of any ofsaid groups, and means responsive to said frame generating means toenable said transmitter at the beginning of each of said frames inresponse to said identifiable signal characteristic of said one channelof a first frame and to disable said transmitter after the end of one ofsaid frames in response to the occurrence of said identifiable signalcharacteristic of an immediately following frame, whereby only completeframes of data are transmitted during each of said on conditions.
 4. Aperipheral station according to claim 1, wherein said several conditionsare alarm conditions, wherein said means for deriving a signal inresponse to the occurrence of an alarm condition is responsive to anyone of several alarm condition detectors at the peripheral station,wherein one of said channels has a time duration identifying the alarmcondition occurring at the peripheral station, and wherein the timedurations of the remaining channels of each frame are digitallyindicative of the identification of the transmitting peripheral station.5. A peripheral station according to claim 4, wherein said framegenerating means generates a plurality of time spaced pulses during eachframe, corresponding portions of adjacent ones of said pulses defining adata channel, the time duration of a first channel of each frame beingindicative of the alarm condition occurring at the peripheral station,and said means for providing an identifiable signal characteristic toone of said channels provides said signal characteristic to the firstchannel and includes code generator means responsive to the output of analarm condition detector sensing an alarm condition, said several alarmcondition detectors each including time constant circuit meansconNectable to said code generating means in response to the occurrenceof an alarm condition to condition said code generating means to producepulses defining a channel of a duration indicative of the sensed alarmcondition.
 6. A peripheral station according to claim 5, wherein saidchannel generating means further includes number generator means forgenerating pulses defining channels of durations indicative of a pluralnumber numerical identification of the peripheral station.
 7. A radioalarm system, comprising geographically separated transmitter means fortransmitting groups of information bearing frames separated by inactiveperiods each enduring about twice as long as one of said groups ofinformation bearing frames, wherein said frames deriving from separateones of said geographically separated transmitters are of randomrelative lengths, means for initiating transmissions of said informationgroups from separate ones of said transmitters at random times, andmeans for limiting the time of a transmission from any one of saidtransmitters to only but not less than several minutes, wherein isprovided means for terminating said transmissions only in response tocompletion of one of said frames.
 8. In an alarm transmitter, means fortransmitting a group of successive information bearing frames, saidmeans including means responsive to occurrence of a random event forgenerating a pulse of first duration for all said frames, meansresponsive to completion of said pulse for generating a time quantizedsignal representing by its duration the character of said random event,means responsive to completion of said signal for generating asequential plurality of further time quantized signals having together amulti-digit significance, and means terminating each of said frames withone of said pulses of first duration constituting the initial pulse of asucceeding frame for all except the last frame of said group.
 9. In analarm system, a satellite radio station including a plurality ofcondition detector circuits, means responsive to detector circuits forinitiating transmission of a pattern of information bearing pulseposition modulated frames from said satellite radio station, the firstpulse ofeach of said frames having a characteristic distinguishing saidfirst pulse from all other pulses of said frames, means responsive tothe one of said condition detector circuits which detects an alarmcondition for generating a second pulse separated from said first pulseby a time interval equal to a multiple of a basic time interval, saidmultiple identifying said one of said condition detector circuits, meansresponsive to said second pulse for generating further pulses eachseparated from the pulse preceding itself by a time interval which isdigitally decimally coded in terms of said basic time interval, the lastof said further pulses being said first pulse of a succeeding frame andhaving said characteristic and the coding of said decimally coded pulsesidentifying said satellite radio station in terms of a multi-digitnumber.
 10. The combination according to claim 9, wherein is providedmeans for transmitting said frames in a period of several minutes only,said period consisting of groups of said frames separated by silentintervals unoccupied by said frames on at least a 20 percent duty cyclebasis, and means for terminating said period only in response totermination of one of said frames.
 11. The combination according toclaim 9, wherein is further included a central station having meansresponsive to said frames to record in response to each of said frames arecord of the identity of said satellite station and the identity ofsaid adverse condition, and means for disabling said means to record inresponse to reception of an abnormal format of one of said frames. 12.In a satellite alarm system, plural satellite stations each including anassociated normally unenergized radio transmitter, an alarm conditionsensing system at each station, means responsive to sensing of an alarmby said alarm condition sensing system for energizing the associatedtransmitter for a predetermined time interval of the order of severalminutes, said transmitter including means for transmitting informationbearing time position modulated plural pulse frames during said timeinterval, each of said frames including a master pulse of the sameduration, and means for terminating said time interval only incoincidence with occurrence of one of said master pulses, said masterpulses each defining concurrently the beginning of one frame and thetermination of a preceding frame, said frames including plural pulsesseparated by information bearing digitally coded spaces which arediverse for different ones of said satellite stations and serve asidentification of said satellite stations.
 13. The combination accordingto claim 12, wherein said means for energizing includes means foralternately energizing and then de-energizing said transmitterperiodically for groups of plural successive integral frames during saidpredetermined time interval with an on the order of a 33 percent dutycycle, and means for initiating and terminating each of said groups ofplural frames during which said transmitter is energized only incoincidence with master pulses.